RF Switch Design/Layout Engineer

RF Switch Design Engineer / Layout EngineerBeRex Corporation (Korea) / BeRex Inc. (USA) Hiring Locations
• Seoul, South Korea – BeRex Corporation
• Santa Ana, California, USA – BeRex Inc. About the PositionBeRex is seeking qualified engineers for two positions: RF Switch Design Engineer and Layout Engineer, at our offices in South Korea and the United States. We welcome candidates at various experience levels, including Junior, Senior, and highly experienced or retired engineers. Applicants may apply for either position based on their area of expertise. Experience in both RF Switch design and IC layout is not required. 1.

Key Responsibilities
Position A: RF Switch Design Engineer
• Design and simulate RF Switch MMIC circuits, including SPST, SPDT, SPnT, DPDT, high-power RF switches, and antenna switches.
• Perform schematic design, transistor stacking, gate bias/control circuit design, impedance matching, and RF performance optimization.
• Support MMIC layout design, DRC/LVS verification, parasitic optimization, and EM simulation.
• Optimize RF performance, including insertion loss, isolation, return loss, switching time, power handling (P0.1dB/P1dB), linearity (IIP3), harmonics, and ESD robustness.
• Conduct on-wafer RF measurements, S-parameter characterization, high-power testing, and silicon validation.
• Analyze and correlate simulation results with silicon measurement data.
• Participate in the full product development cycle from specification definition and circuit design to tape-out, qualification, and mass production.
• Support patent development, invention disclosures, and technical documentation. Position B: Layout Engineer
• Perform RF/Analog MMIC layout design, including floorplanning, device placement, routing, and layout optimization.
• Conduct DRC, LVS, ERC, and PEX verification in compliance with foundry design rules.
• Optimize RF signal routing, grounding, shielding, device matching, isolation, and parasitic effects.
• Perform or support EM simulation of RF interconnects, inductors, transmission lines, and passive structures.
• Optimize device layouts for RF transistors, stacked FETs, differential structures, and matching-sensitive devices.
• Prepare final layout databases (GDSII/OASIS), support tape-out verification, and resolve foundry-related issues.
• Collaborate with RF MMIC circuit designers to improve layout performance and support silicon debugging.
• Participate in product development from initial layout through silicon validation and mass production support.
• Support patent development and invention disclosures related to RF layout structures and optimization techniques. 2. QualificationsGeneral Requirements
• Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, Semiconduct